IBM 7030 Stretch | 1961

 

The IBM 7030, known as Stretch, was IBM's first transistorized supercomputer and the fastest computer in the world from 1961 to 1964. Originally designed at the request of Edward Teller for Lawrence Livermore National Laboratory, the first model was delivered to Los Alamos National Laboratory in 1961, followed by a customized version, the IBM 7950 Harvest, delivered to the National Security Agency in 1962. The Stretch at the Atomic Weapons Research Establishment in Aldermaston, England, was extensively used by researchers, but it only gained traction after the development of the S2 Fortran Compiler, which was the first to introduce dynamic arrays and was later ported to the Ferranti Atlas at the Atlas Computer Laboratory.

The 7030 was much slower than expected and failed to meet its aggressive performance goals. IBM was forced to reduce its price from $13.5 million to $7.78 million and subsequently withdrew the product from further sales. PC World magazine named Stretch one of the biggest project management failures in IT history.

Within IBM, it was difficult to accept being overshadowed by the smaller Control Data Corporation (CDC). Project leader Stephen W. Dunwell was initially made a scapegoat for the "failure," but he received an official apology when the success of the IBM System/360 became apparent, and in 1966 he was appointed an IBM Fellow.

Despite failing to meet its performance targets, Stretch laid the groundwork for many design features in the successful IBM System/360, announced in 1964.

In early 1955, Dr. Edward Teller sought a new scientific computing system for three-dimensional hydrodynamic calculations. IBM and UNIVAC were solicited for proposals for this new system, called the Livermore Automatic Reaction Calculator (LARC). IBM estimated the cost at around $2.5 million with a performance target of 1 to 2 MIPS. In May 1955, Livermore announced that UNIVAC had won the LARC contract.

In September 1955, fearing that Los Alamos National Laboratory might also place an order for a LARC, IBM submitted a preliminary proposal for a high-performance binary computer. In January 1956, the Stretch project was formally initiated, and by November 1956, IBM had secured a contract with an aggressive performance goal of being at least 100 times faster than the IBM 704 (i.e., 4 MIPS), with delivery scheduled for 1960.

During the design phase, it became necessary to reduce clock speeds, making it clear that Stretch would not meet its aggressive performance targets. By 1960, the IBM 7030 was priced at $13.5 million, but actual benchmarks in 1961 indicated its performance was only about 30 times that of the IBM 704 (i.e., 1.2 MIPS), causing considerable embarrassment for IBM. In May 1961, Thomas J. Watson Jr. announced a price cut to $7.78 million for all 7030s under negotiation and immediately withdrew the product from further sales.

Although the IBM 7030 was not deemed successful, it led to the development of many technologies integrated into later successful machines. The Standard Modular System transistor logic formed the basis for the IBM 7090 line of scientific computers, the IBM 7070 and 7080 business computers, the IBM 7040 and IBM 1400 lines, and the IBM 1620 small scientific computer; the 7030 utilized about 170,000 transistors. Concepts such as multiprogramming, memory protection, generalized interrupts, and the eight-bit byte for I/O were later incorporated into the IBM System/360 line and most subsequent central processing units (CPUs).

Stephen Dunwell, who became a scapegoat after Stretch's commercial failure, emphasized that many core concepts of the System/360 were pioneered by Stretch following the successful launch of System/360 in 1964. By 1966, he had received an apology and was appointed an IBM Fellow.

Techniques such as instruction pipelining, prefetching and decoding, and memory interleaving were utilized in later supercomputer designs like the IBM System/360 Models 91, 95, and 195, as well as the IBM 3090 series. These techniques continue to be used in advanced microprocessors, starting with the 1990s generation, including the Intel Pentium and Motorola/IBM PowerPC, as well as in many embedded microprocessors and microcontrollers from various manufacturers.

The IBM 7030 CPU employed emitter-coupled logic (originally known as current-steering logic) on 18 types of Standard Modular System (SMS) cards. It consisted of 4,025 double cards and 18,747 single cards, housing a total of 169,100 transistors and consuming approximately 21 kW of power. It used high-speed NPN and PNP germanium drift transistors with a cutoff frequency exceeding 100 MHz, each consuming around 50 mW.

Some third-level circuits utilized a third voltage level, with each logic level introducing a delay of about 20 ns. To enhance speed in critical areas, emitter-follower logic was employed to reduce the delay to approximately 10 ns. The 7030 utilized the same core memory as the IBM 7090.