ILLIAC IV | 1965

 ILLIAC IV was the first large-scale parallel computer, designed with 256 64-bit floating-point units (FPUs) and 4 central processing units (CPUs). The system was initially intended to process one billion operations per second, but due to budget issues, only a single "quadrant" with 64 FPUs and one CPU was built. All FPUs were designed to process the same instruction, such as addition (ADD), subtraction (SUB), etc. This system can be classified as a Single Instruction, Multiple Data (SIMD) architecture by modern standards.

The idea of creating this machine stemmed from Daniel Slotnick's work as a programmer on the IAS machine in 1952. The actual design work began in 1960 when Slotnick, working at Westinghouse Electronics, secured funding from the U.S. Air Force. However, after funding ended in 1964, Slotnick moved to the University of Illinois at Urbana-Champaign and joined the ILLIAC team. With additional support from the U.S. Defense Advanced Research Projects Agency (ARPA), development shifted from the original design with 1,024 1-bit processors to a new design with 256 64-bit processors.

As the machine was being assembled, the university began constructing a new facility to house it. However, due to political tensions surrounding funding from the U.S. Department of Defense, ARPA and the university grew concerned about the machine's safety. As a result, when the first 64-processor quadrant was completed in 1972, it was sent to NASA's Ames Research Center, where it underwent three years of modifications to fix various defects. In November 1975, ILLIAC IV was connected to ARPANET, making it the first supercomputer to be networked, nearly 12 months ahead of the Cray-1.

Although it operated at half the intended speed, the ILLIAC IV, consisting of 64-processor quadrants, achieved a performance of 50 MFLOPS, making it the fastest computer in the world at the time. It was also known as the first large computer to use semiconductor memory and was considered one of the most complex computers ever, with over one million gates. Despite being generally regarded as a failure due to budget overruns, the design of ILLIAC IV played a key role in the development of new programming techniques and system development for parallel systems. In the 1980s, the concept of ILLIAC IV contributed to the successful delivery of several machines.

In June 1952, Daniel Slotnick began working on the IAS machine at the Institute for Advanced Study (IAS) at Princeton University. The IAS machine featured a bit-parallel arithmetic logic unit (ALU) that processed 40-bit words. Initially, it had a Williams tube memory, which was later supplemented by an engineering research associates (ERA) magnetic drum. This drum had 80 tracks and could read two words simultaneously, with each track storing 1,024 bits.

While thinking about this drum mechanism, Slotnick questioned the right way to build a computer. He wondered if, instead of writing the bits of a word in parallel across 40 tracks, they could be written serially on a single track, allowing the machine to directly read the bits from the drum and process them in a bit-serial fashion. This design would still have multiple tracks and heads, but each track would read one bit at a time and pass it to a parallel ALU for processing. This would make the system a bit-serial, word-parallel computer.

Slotnick proposed this idea at IAS, but John von Neumann dismissed it, saying "too many tubes are needed." Slotnick left IAS in February 1954 to return to school for his doctoral studies, and the idea was forgotten.

After completing his Ph.D., Slotnick worked at IBM. At the time, technologies for scientific computation were transitioning from tubes and drums to transistors and magnetic core memory, and the idea of processing data in parallel from drums no longer seemed appealing. However, Slotnick recognized that parallel processing systems could still offer significant performance benefits for certain applications, and in 1958, he co-authored a paper on parallel processing systems with his colleague John Cocke (who would later become famous for inventing RISC).

After a brief period at IBM, Slotnick worked briefly at Aerocar Airlines and then joined the Westinghouse Air Force Division, where he was put in charge of designing a system using 1,024 bit-serial ALUs (processing elements, PEs) through a U.S. Air Force RADC contract. This design was named "SOLOMON" after King Solomon, who was wise and had 1,000 wives.

The SOLOMON system was designed with a master CPU (control unit, CU) receiving commands and transmitting them to the PEs for processing. Each PE had its own memory module for storing operands and results, and a separate network connected the PEs to share results. Initial test systems were configured with 3x3 (9 PEs) and 10x10 models, and more complex designs were considered, but development was halted after a major sponsor from the Air Force died in an accident.

After the SOLOMON project ended, Slotnick joined the ILLIAC team at the University of Illinois at Urbana-Champaign. The university had been designing and building large computers since 1949 with support from the U.S. Department of Defense and ARPA. In 1964, the University of Illinois began the design of a new computer, ILLIAC IV, under a contract with ARPA. ILLIAC IV was the fourth computer developed by the university, and development began in 1965, with the first design completed in 1966.

Unlike SOLOMON's bit-serial concept, ILLIAC IV's PEs were upgraded to 64-bit parallel processors, with 12,000 gates and 2,048 thin-film memory elements. Each PE had 5 64-bit registers, allowing it to perform tasks such as passing data to neighboring PEs. Instead of 1,024 PEs, the new design used 256 PEs divided into four 64-PE quadrants, each with its own independent control unit (CU).

The system, operating at a 25 MHz clock speed, was designed to process one billion floating-point operations per second (1 GFLOPS), making it the fastest computer in the world at the time.

In early 1966, the University of Illinois sent out proposals to recruit industrial partners to build the ILLIAC IV design. Seventeen responses were received, and three partners were selected, with Burroughs ultimately teaming up with Texas Instruments (TI) to build the system. TI used 64-pin ECL (Emitter Coupled Logic) integrated circuits (ICs) to make the system more compact.

However, TI was unable to successfully build the 64-pin design, which caused the system's speed to drop from 25 MHz to 16 MHz. This led to a delay of about two years and an increase in costs by millions of dollars. Additionally, design changes were made to address memory issues, and the machine was ultimately limited to a 64-PE quadrant, reducing the system's speed to approximately 200 MFLOPS.

In 1970, the ILLIAC IV was moved from its original design to NASA's Ames Research Center in California to ensure its safety in the face of student protests and political tensions. The ILLIAC IV, installed at Ames, was completed in 1972, after the project had been delayed by three years and exceeded its budget by six million dollars.

Later, ILLIAC IV was connected to ARPANET and became the first networked supercomputer, playing a key role in the evolution of such machines.